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Welcome
Table of Contents
EECS
EECS
- Table of Contents
- CS 161
  CS 161
  - Table of Contents CS 161
  - Cryptography
    Cryptography
    
    5. Introduction to Cryptography
    
    6. Symmetric-Key Encryption
    
    7. Cryptographic Hashes
  - Memory Safety
    Memory Safety
    
    2. x86 Assembly and Call Stack
    
    3. Memory Safety Vulnerabilities
    
    4. Mitigating Memory-Safety Vulnerabilities
  - Security Principles
    Security Principles
    
    1. Security Principles
- CS 168
  CS 168
  - Table of Contents CS 168
  - 0. Introduction to CS 168
    0. Introduction to CS 168
    
    0. Introduction
  - 1. Overview of Computer Networks and the Internet
    1. Overview of Computer Networks and the Internet
    
    1. Computer Networks and the Internet
  - 2. Application Layer
    2. Application Layer
    
    2. Application Layer
    
    2.0 Key Terms
    
    2.1 Principles of Network Appications
    
    2.2 The Web and HTTP
    
    2.3 Electronic Mail in the Internet
    
    2.4 DNS - The Internet's Directory Service
    
    2.5 Peer-to-Peer File Distribution
  - Lectures
    Lectures
    
    Introduction
    Introduction
    
    2. How the Internet Works - A Bottom-Up View
    
    3. Architectural Principles
    
    4. Designing the Internet
    
    Routing
    Routing
    
    5. Routing Fundamentals
    
    6. Routing Approaches I
    
    7. Routing Approaches II
- CS 61A
  CS 61A
- CS 61B
  CS 61B
  - Table of Contents Table of Contents
    Table of contents
    
    CS 61A: Data Structures
- CS 61C
  CS 61C
  - Table of Contents
  - 0. Introduction to CS 61C
    0. Introduction to CS 61C
    
    0. Introduction
  - 1. Number Representation
    1. Number Representation
    
    1. Number Representation
    
    1.1 Decimal, Binary, and Hexadecmial Number Systems
    
    1.2 Signed Representations
    
    1.3 Floating Point Representation
  - 10. Synchronous Digital Systems (SDS)
    10. Synchronous Digital Systems (SDS)
    
    10. Synchonous Digital Systems (SDS)
  - 11. Finite State Machines (FSMs)
    11. Finite State Machines (FSMs)
    
    11. Finite State Machines
  - 12. RISC V Datapath and Control Logic
    12. RISC V Datapath and Control Logic
    
    12. RISC V Datapath and Control Logic
  - 13. Datapath Performance and Pipelining
    13. Datapath Performance and Pipelining
    
    13. Datapath Performance and Pipelining
  - 14. Operating Systems
    14. Operating Systems
    
    14. Operating Systems (OS)
  - 15. Data and Thread Level Parallelism
    15. Data and Thread Level Parallelism
    
    15. Data and Thread Level Parallelism
  - 16. Caches
    16. Caches
    
    16. Caches
  - 17. Cache Coherency
    17. Cache Coherency
    
    17. Cache Coherency
  - 18. Virtual Memory
    18. Virtual Memory
    
    18. Virtual Memory
  - 19. Dependability
    19. Dependability
    
    19. Dependability
  - 2. C Programming
    2. C Programming
    
    2. C Programming
    
    2.1 C Similarity to Java Syntax
    
    2.2 Memory Allocation
    
    2.4 Pointers and Arrays
    
    2.2 Stack, Heap, Static, Code
  - 3. Memory
    3. Memory
    
    3. Memory
    
    3.1 Sizes of Types, Casting
    
    3.2 Memory Alignment
    
    3.3 Endianness
  - 4. More C Programming
    4. More C Programming
    
    4. More C Programming
    
    4.1 Higher Order Functions in C
    
    4.2 Structs and Unions
    
    4.3 Defines
    
    4.4 Programming in C
  - 5. RISC V Programming
    5. RISC V Programming
    
    5. RISC-V Programming
    
    5.1 RISC V Registers
    
    5.2 Arithmetic and Bitwise Operators
    
    5.3 Branching
    
    5.4 Loads and Stores
    
    5.5 Other RISC V Instructions
  - 6. RISC V Calling Convention
    6. RISC V Calling Convention
    
    6. RISC-V Calling Convention
    
    6.1 RISC V Register Names
    
    6.2 The Stack Pointer, Callee, Caller Conventions
    
    6.3 An Example RISC V Code with Calling Convention
    
    6.4 Recursive Functions in RISC V
  - 7. RISC V Instruction Formats
    7. RISC V Instruction Formats
    
    7. RISC-V Instruction Formats
    
    7.5 Self-Modifying Code
  - 8. Compiler, Assembler, Linker, Loader (CALL)
    8. Compiler, Assembler, Linker, Loader (CALL)
    
    8. Compiler, Assembler, Linker, Loader (CALL)
  - 9. Combinatorial Logic, Boolean Algebra
    9. Combinatorial Logic, Boolean Algebra
    
    9. Combinatorial Logic, Boolean Algebra
- EECS 151
  EECS 151
  - Table of Contents
  - 1. Introduction
    1. Introduction
    
    1. Introduction to EECS 151
  - 2. Design Abstraction
    2. Design Abstraction
    
    2. Design Abstraction
  - 3. Metrics and Verilog
    3. Metrics and Verilog
    
    3. Metrics and Verilog
  - 4. Verilog II
    4. Verilog II
    
    4. Verilog II
  - 5. Combinational Logic I
    5. Combinational Logic I
    
    5. Combinational Logic
  - 6. Combinational Logic II
    6. Combinational Logic II
    
    6. Combinational Logic II and FSM I
  - 7. Finite State Machines
    7. Finite State Machines
    
    7. Finite State Machines
  - 8. RISC V Datapath I
    8. RISC V Datapath I
    
    9. RISC-V Datapath I
  - 9. RISC V Datapath II
    9. RISC V Datapath II
    
    9. RISC-V Datapath II
  - A. .Verilog
    A. .Verilog
    
    A. Verilog
- EECS 16A
  EECS 16A
  - 0. Introduction
  - Table of Contents
Physics
Physics
- Table of Contents
- Physics 137A
  Physics 137A

Table of Contents¶

CS 61A: Data Structures¶

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