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1. Introduction to EECS 151

This note is about the first lecture in EECS 151, taught by Professor Sophia Shao.

Class Goals

Introduction to digital integrated circuit and system engineering. The key concepts needed to be a good digital system designer, and discover your own creativity.

Learn abstractions that allow reasoning about design behavior. Manage design complexity through abstraction and understanding of tools. Allow analysis and optimization of the circuit's performance, power, cost, etc.

Learn how to make sure your circuit and system works. There are way more ways to mess up a chip than to get it right.

Course Focuse

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Prerequisites

CS 61C - C, Boolean Logic, RISC-V ISA

  • Will review combinational and sequential logic and RISC-V datapath, pipelining (but in more depth)

EECS 16A/B - Digital gates, RC networks

  • We will review transistor operation and design of CMOS logic

Follow-Up Courses

CS 61C --> EECS 151 --> CS 152 --> any graduate-level course in architecture/digital systems

EECS 151 + EE 140 is a springboard into integrate circuits

Tapeout class: EE 194 (special topic course), spring semester class.

Bringout class: follow-up to tapeout, where the chip is produced and then we test it.

Prerequisites for tapeout and bringout: EECS 151 or EE 140. 152 not required. Divide and conquer approach, so your background will be what you design.

RISC-V 32-bit ISA

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End of EECS 151

You wiill be able to build a complex digital syste

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Administrativia

Lectures:

  • Slides available before lecture, lectures recorded, posted after lecture.

Textbooks:

  • Digital Design and Computer Architecture, Digital Integrated Circuits: A Design Perspective, CMOS VLSI Design

Discussions:

  • Start next Friday. Review of important concepts from lecture, help with problem sets.

Homework:

  • Roughly 10 problem sets. Posted on Thursday, Due Friday, 8 days later

  • Essential to understanding of material

  • Late policy: 7 days for problem sets, 20% point reduction per day after slip day

  • Solutions poster the week after due date

Labs:

  • Late policy: 14 slip days for labs, 20% point reduction per day after slip day

  • 6 lab exercises, done solo. Lab report due by next lab session

  • 7 week design project, done with partner. Project demo/interview RRR week, project report due RRR week

  • Both labs: you will learn Verilog. The design component is the same. The tooling is different. Also different in how to interpret report using the different applications and tools.

Midterm + Final

  • Midterm: Late October 7-9pm

  • Final: Wed, 12/14, 8-11am

  • No alternative midterm/final. But may allow students to take the final right after the official slot.

  • All exams are closed book with one double sided sheet of notes on midterm, two for the final.

Clobber:

  • Override your midterm score with the score on the final if you perform better on the final

  • The reverse is not true - you must take the entire final exam, regardless of your score

Class is not curved.

Tips on How to Get a Good Grade

The lecture material is not the most challenging part of the couse. You should be able to understand everything as we go along. Do not fall behind in lecture and tell yourself you "will figure it out later from the notes or book". Slides will be online before the lecture. Study them before class. Ask question in class and stay involved in the class - that will help you understand. Come to OH to check your understanding or to ask question. Complete all the homework. Take labs very seriously.

Digital Integrated Circuits and Systems: Past, Present, and Future

People tend to think of HW as an independent topic, but it is always interconnected with software. Hardware drives software. There are connections to the entire stack and different markets

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Moore's Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 12 months. He made a prediction that semiconductor technology will double its effectiveness every 12 month. Now it has changed to about every 24 months.

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How can we reduce the cost to fabricate more transistors? It is still there in that we are getting more transistors, but the cost is not going down. That is where people say it is dying.

We look at the density: transistors/unit area. It has been growing consistently.

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Cost is the biggest challenge to deal with to uphold Moore's law

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The Other Trends Power!

Dennard Scaling (1974)

Voltages (and currents) should be scaled proportionally to the dimensions of the transistor. And, in theory, power density constant!

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How we can make smaller transistors with same power density.

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The Other Demon: Design Cost

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Get to next section:

2. Design Abstraction