4. Verilog II¶

Review¶

Design metrics: 1. Functionality and robustness 2. Cost 3. Performance 4. Power and Energy

Verilog: 1. Hardware Description language 2. Logic synthesis: Verilog -> Gate-level netlists 3. Used in both ASIC and FPGA

Verilog Introduction¶

A module definition describes a component in a circuit. There are two ways to describe module contents 1. Structural Verilog

List of sub-components and how they are connected
Just like schematics, but using text
Tedious to write, hard to decode
You get precise control over circuit details
May be necessary to map to special resources of the FPGA/ASIC
Behavioral Verilog
Describe what a component does, not how it does it
Synthesized into a circuit that has this behavior
Result is only as good as the tools

The idea is to build up a hierarchy of modules. Top-level module is your entire design (or the environment to test your design)

Verilog Modules and Instantiation¶

Modules define circuit components. Instantiation defines hierarchy of design:

4.1 modulesyntax.png

A module is not a functio in the C sense. Ther eis no call and return mechanism. Think of it more like a hierarchical data structure.

Here is an example: XOR

4.2 xor model.png

Note that the instantiated gates are not executed. They are active always. The xorgate already exists as a built-in (so really no need to define it). Undeclared variables assumed to be wires. Don't let this happen to you!

Simple Behavioral Model¶

4.3 simplebehavioralmodel.png

The assign statement has a bitwise "and" gate. The assignment continuously happens, therefore any change on the RHS is reflected in out immediately (except for small delay associated with the implemnetaion of the practical &.)

It is not like an assignment in C that takes place when the program counter gets to that place in the program.

Instantiation, Signal Array, Named Ports¶

4.4 instantsignalarraynamedports.png

Example: Ripple Adder¶

4.5 rippleadder.png

Verilog Operators¶

A.2 operators.png

A.3 operators2.png

A.4 operators3.png

Continuous Assignment Examples¶

Assign values whenever there is a change in the RHS. Model combinational logic without specifying an interconnection of gates:

4.6 continuousassignment.png

Non-Continuous Assignmnets¶

This is a bit unusual from a hardware specification point of view. However it shows that Verilog is a simulation language

4.7 noncontinuous.png

Always Blocks¶

Always blocks give us some constructs that are impossible or awkward in continuous assignments

4.8 mux.png

4.9 muxif.png

Simplified Verilog Guidelines¶

For combinational logic: - Continuous assignment: assign a = b & c

Always block with @(*):

always @(*) begin
    a = b & c; // blocking statement
end